My invention relates to data transmission systems and, particularly, to method and means for synchronizing the data transfer between such systems.
In such systems of the synchronous type, it is known that a clock at a receiving site must be synchronized with the clock at a transmitting site, or other means provided for compensating for the lack of synchronization in order that data pulses be adequately communicated between the sites. It is common practice, for example, to utilize a phase-locked loop, wherein a receiver clock is synchronized with a transmitter clock by recovering timing information from the incoming pulses for controlling the frequency and phase of the receiver clock. One such synchronizing technique is analyzed in an article by C. J. Byrne in the Bell System Technical Journal, Vol. 41, 1962, at page 559. Another method of synchronizing clocks at a plurality of sites which communicate with each other involves what is called phase or frequency averaging. At each location the clock is synchronized to the average of the frequency and phase of each of the pulse streams arriving from each of the other sites. This technique is discussed briefly by J. S. Mayo in the Bell System Technical Journal, Vol. 44, 1965, beginning at page 1813.
The foregoing techniques typically involve the use of analog circuitry which may be difficult to control and expensive in that separate phase-locking circuitry is required for each transmission line incoming to a receiving site, W. K. L. Chang et al in their U.S. Pat. No. 3,484,555 of Dec. 16, 1969, disclose a digital phase locking circuit for overcoming some of the disadvantages of the analog counterpart. They provide an independent oscillator at the receiver and a counter for counting the signals from the oscillator, the output of which provides the clock signals for sampling the incoming pulses. The counter output is controlled for synchronization with the pulses by circuitry which responds to transistions of the pulses for either advancing or retarding the count state of the counter. Thus, their receiver clock is derived from the incoming pulse stream so as to lock the clock to the frequency and phase of the pulses.